1. Field of the Invention
The field of the invention relates to a ferroelectric memory device and, more particularly, to a reference voltage generating circuit for generating a reference voltage capable of reading data from ferroelectric memory cells.
2. Description of the Related Art
Nonvolatile memory continuously stores data even after a memory power source is cutoff. Ferroelectric memory employing ferroelectric materials, such as lead zirconium titanate (PZT), have a hysteresis characteristic capable of not only providing non-volatility but also low power consumption and speedy operation.
A ferroelectric memory is typically constructed of a ferroelectric capacitor and an access transistor. When voltage is applied to the ferroelectric capacitor, ferroelectric material is polarized according to the direction of the applied electric field, and a logic state “1” or “0” is stored in conformity with the electrical polarization. An IT/IC ferroelectric memory cell stores data using a switching region for data “1” and a non-switching region for data “0”. In order to read the data stored in the memory cell, a first voltage is applied to the ferroelectric capacitor and a second voltage is supplied to a bit line, where the bit line voltage is compared with a reference voltage to read the data of the memory cell as a logical “1” or “0”. Thus, the ferroelectric memory requires a reference voltage generating circuit for generating the reference voltage. A nonvolatile memory device having a dummy cell circuit to generate a reference voltage is disclosed in U.S. Pat. No. 6,574,133 entitled “Nonvolatile ferroelectric memory device having dummy cell circuit.”
FIG. 1 illustrates the voltage generating circuit disclosed in U.S. Pat. No. 6,574,133 and FIG. 2 is a timing diagram of the reference voltage generating circuit referred to in FIG. 1.
Referring to FIG. 1, a voltage generating circuit is comprised of a memory cell array,                a sense amplifier 2, and a bit line voltage control circuit 3. The memory cell array is composed of memory cells MC0 and MC1, each comprised of a ferroelectric capacitor FC0 and FC1 and an access transistor MQ0 and MQ1, respectively. One end of ferroelectric capacitors FC0 and FC1 is connected to plate lines PL0 and PL1, respectively, while another end is connected to bit lines /BL and BL through NMOS transistors MQ0 and MQ1, respectively. Each gate of the NMOS transistors MQ0 and MQ1 is connected to word lines WL0 and WL1, respectively.        
Bit lines /BL and BL are connected to a sense amplifier 2 at sense node /BLSA and BLSA through NMOS transistors Q01 and Q02, respectively, when NMOS transistors Q01 and Q02 are selected by signal PHT. Sense amplifier 2 is coupled to bit line voltage control circuit 3 at sense node /BLSA and BLSA. Sense amplifier 2 is enabled by enable signal SEN.
Bit line voltage control circuit 3 is capable of controlling the voltage in bit lines /BL and BL, and includes a coupling capacitor C, NMOS transistors Q11 and Q12, and a reset NMOS transistor Q13. NMOS transistors Q11 and Q12 are coupled between coupling capacitor C at node N and sense nodes BLSA and /BLSA, respectively. When selected by control signals OSWL0 and OSWL1, respectively, NMOS transistors QI1 and Q12 couple a corresponding bit line with coupling capacitor C in order to lower the potential of the corresponding bit line. The reset NMOS transistor Q13 resets the voltage at node N when selected with a reset signal OSRST. Another end of the coupling capacitor C is connected to a drive signal OSDRV.
Referring to FIG. 2, a timing diagram shows a reading operation of memory cell MC0 of the voltage generating circuit. Prior to the execution of the reading operation, reference voltage generating circuit 3 is in a stand-by mode, where a reset signal OSRST is applied as a logical “H”, and control signals OSWL0 and OSWL1 are applied as a logical “L”. During stand-by mode, node N is maintained as 0V, coupling capacitor C is charged to Vaa·C by drive signal OSDRV of logical “H”, and the bit line voltage of bit line /BL is precharged to Vss.
When performing a read operation, at time t0, reset transistor Q13 is turned off by a logical “L” of the reset signal OSRST, and at time t1, word line WL0, plate line PL0, signal PHT and control signal OSWL0 are simultaneously applied as a logical “H”. As a result, transistor Q11 is turned on, and capacitor C is coupled to the sense node /BLSA, and bit line /BL. The bit line voltage of bit line /BL is consequently increased, where the magnitude of the increase is dependent on the logic state “1” or “0” stored by memory cell MC0. At time t2, drive signal OSDRV becomes a reference voltage of 0V by a logical “L” requiring the voltage at node N to become—Vaa, and thus lowering the voltage of bit line /BL and sense node /BLSA. At time t3, enable signal SEN is applied as a logical “H”, enabling sense amplifier 2 to read data based on the voltage level at sense node /BLSA.
Accordingly, to read data from a memory cell that is constructed of one ferroelectric capacitor and one access transistor, a reference voltage generating circuit requires one coupling capacitor and three NMOS transistors for every sense amplifier. In order to generate a reference voltage having a medium voltage level, between the voltages corresponding to the logic states “1” and “0” of the data stored in ferroelectric memory cells, the capacitance and size of the coupling capacitor must increase, and thus the size of the reference voltage generating circuit must also increase. Furthermore, high integration of a ferroelectric memory device comprising a plurality of memory cells becomes difficult due to the size increase of the reference voltage generating circuit required to read the cells.